1. Field of the Invention
The present invention relates to a semiconductor wafer (hereinafter, referred to as a wafer) in which a semiconductor device is formed, a novel semiconductor device exhibiting less variation in a transistor characteristic, and a method for manufacturing the same.
2. Description of the Related Art
A wafer formed of silicon or germanium, which is used for a semiconductor device, has heretofore been manufactured usually by slicing a cylindrical ingot that is grown by a single crystal growth method such as a high frequency induction-heating method or a pulling-up method. A plurality of processed semiconductor integrated circuits are formed on a principal plane of the wafer which has been formed from the ingot. Thereafter, the wafer is cut along scribe lines into chips in which an integrated circuit area is formed, and the chips are separated from each other.
FIG. 1 is a section view showing a conventional semiconductor device formed in a semiconductor substrate. The semiconductor device is formed on a wafer, and the wafer is cut into chips in which an integrated circuit is formed. The chips are finally separated from each other. Accordingly, FIG. 1 is a section view of the chip, and especially illustrates a chip formed in a portion of the wafer, which is close to an external peripheral surface and a peripheral region where no integrated circuit is formed. A semiconductor substrate 1 is, for example, a p-type silicon semiconductor. The left side of FIG. 1 is an external peripheral portion of the wafer and a peripheral portion thereof, and in these portions the surface of the semiconductor substrate 1 is exposed for the reason described later. An inner portion of the external peripheral portion and the peripheral portion, that is, a central portion and a right side, show a chip region. In the chip region, an element isolation region 2 formed of silicon dioxide (SiO2), which has a Shallow Trench Isolation (STI), is formed by a Local Oxidation of Silicon (LOCOS) method. N-type source/drain regions 3 are formed in an element region partitioned by the element isolation region 2. A gate electrode 5 formed of polysilicon or the like is formed by a thermal oxide method on a portion of a gate insulating film formed of a silicon oxide film, the portion thereof being located between the source/drain regions 3. The gate insulating film 4 is formed on the entire surface of the semiconductor substrate 1, and, on the semiconductor substrate 1, a silicon oxide film is formed so as to cover the gate electrode 5.
The silicon oxide film is subjected to an anisotropic etching such as an RIE (Reactive Ion Etching) and processed to a side wall insulating film 6 left on the side wall of the gate electrode 5. Subsequently, on the semiconductor substrate 1, an interlayer insulating film 7 formed of such as BPSG (Boron-doped Phospho-Silicate Glass) is deposited, and flattened. A contact hole which communicates with one of the source/drain regions 3 is formed in the interlayer insulating film 7, and a connection wiring 8 formed of such as tungsten,for example (W) is filled in the contact hole. A metal film formed of copper (Cu) is deposited on the flattened surface of the interlayer film 7, and patterned, thus forming a copper wiring 9 electrically connected to the connection wiring 8. On the copper wiring 9, a protection insulating film can be formed, or a plurality of copper wirings can be formed interposing the interlayer insulating film during the formation of the protection insulating film.
The above-described copper wiring technology used for semiconductor devices has been involved in a problem that diffusion of copper into a silicon wafer is seriously anxious for.
In the conventional copper wiring technology, copper is principally covered with a barrier film such as Ta, TiN and SiN. However, copper may attach to a wafer edge and a rear surface of the wafer during formation of the barrier film, or the copper may attach to them from a manufacturing apparatus and a wafer carrier. Since resist is usually removed from the wafer edge by about 1 to 3 mm before the time of patterning the wafer, the surface of the semiconductor substrate corresponding to the portion where the resist is removed is exposed after an etching treatment.
A SiN film is formed on a region where transistors are formed, so that the diffusion of the copper into that region can be prevented. However, the silicon substrate formed of silicon is exposed in its rear surface and its wafer edge portion, and in such situation, when the wafer is subjected to the copper processing step, the copper diffuses into a chip from the external periphery of the wafer, so characteristics of the transistors formed in the chip may vary.
To be more specific, with regard to the conventional semiconductor substrate, for example, a silicon wafer is formed of only silicon. In order to prevent the attachment of resist to the carrier, the resist of the periphery portion of the wafer is removed in manufacturing steps of the semiconductor device using such wafer, especially in a lithography step as described above. Accordingly, since the wafer edge portion is always exposed to etching atmosphere, so that the silicon substrate comes to be exposed. As a result, the contamination of the semiconductor substrate due to the attachment of the copper to the silicon portion in forming the copper wiring occurs as described above. Furthermore, there has been a problem that when a high concentration semiconductor substrate having a p-type epitaxial silicon semiconductor layer formed therein (p-epi on p+ substrate) is employed, impurities diffuse to the outside of the semiconductor substrate during a thermal step.
The present invention was made in view of the foregoing circumstances, and the object of the present invention is to provide a wafer which prevents a diffusion of copper to silicon due to a thermal treatment such as a copper wiring formation step and lessens the variations in transistor characteristics, a method for manufacturing the same, and a semiconductor device formed of the same.
The present invention is featured by forming a protection insulating film in a peripheral area (peripheral portion) of a principal plane of the wafer, an external side plane and a rear plane, which prevents a diffusion of copper to the inside of the wafer, specifically a protection insulating film formed of a material having a small Cu diffusion coefficient. The protection insulating film prevents the copper that is a wiring material from diffusing into a chip formation region of the wafer, and controls the changes of transistor characteristics caused by the Cu diffusion.
The wafer of the present invention is first characterized in that the wafer has a semiconductor wafer having a first plane where an integrated circuit is formed, a second plane and a peripheral area, and a protection film formed in the second plane and the peripheral area. The wafer of the present invention is secondly characterized in that the wafer has a semiconductor wafer having a first plane where an integrated circuit is formed, a second plane and a peripheral area, and a protection film formed of silicon nitride, which is formed in the second plane and the peripheral area.
A first aspect of a method for manufacturing the wafer of the present invention is that the method comprises the step of: forming a protection film on a first plane having an integrated circuit formed therein, a second plane and a peripheral area of a semiconductor wafer; and removing the protection film in a region forming the integrated circuit on the first plane. A MOS transistor which has a gate electrode having a side wall insulating film on its side wall is included in the integrated circuit. The foregoing protection insulating film may be formed in the step for forming this side wall insulating film.
Furthermore, a second aspect of the method for manufacturing the wafer of the present invention is that the method comprises the steps of: growing a cylindrical semiconductor single crystal ingot; forming a protection insulating film in a surface of the single crystal ingot, the protection insulating film preventing a diffusion of copper into the interior of the single crystal ingot; and slicing the single crystal ingot, thereby forming a plurality of semiconductor wafers, each having an external side plane, in which the protection insulating film is formed. The second aspect of the method for manufacturing the wafer of the present invention may comprises a step for forming a protection insulating film which extends to the external side plane and prevents the diffusion of the copper to the interior of the semiconductor wafer.
A semiconductor device of the present invention comprises a semiconductor chip having a first plane where an integrated circuit is formed and a second plane, the integrated circuit formed in the first plane; and a protection insulating film formed on the entire surface of the second plane.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.